Very Low Voltage (VLV) Design

被引：5

作者：

Bertran, Ramon ^{[1
]}

Bose, Pradip ^{[1
]}

Brooks, David ^{[2
]}

Burns, Jeff ^{[1
]}

Buyuktosunoglu, Alper ^{[1
]}

Chandramoorthy, Nandhini ^{[1
]}

Cheng, Eric ^{[3
]}

Cochet, Martin ^{[1
]}

Eldridge, Schuyler ^{[1
]}

Friedman, Daniel ^{[1
]}

Jacobson, Hans ^{[1
]}

Joshi, Rajiv ^{[1
]}

Mitra, Subhasish ^{[3
]}

Montoye, Robert ^{[1
]}

Paidimarri, Arun ^{[1
]}

Parida, Pritish ^{[1
]}

Skadron, Kevin ^{[4
]}

Stan, Mircea ^{[4
]}

Swaminathan, Karthik ^{[1
]}

Vega, Augusto ^{[1
]}

Venkataramani, Swagath ^{[1
]}

Vezyrtzis, Christos ^{[1
]}

Wei, Gu-Yeon ^{[2
]}

Wellman, John-David ^{[1
]}

Ziegler, Matthew ^{[1
]}

机构：

[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

[2] Harvard Univ, Cambridge, MA 02138 USA

[3] Stanford Univ, Palo Alto, CA 94304 USA

[4] Univ Virginia, Charlottesville, VA USA

来源：

2017 IEEE 35TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) | 2017年

关键词：

low power design; voltage scaling; frequency scaling; real-time performance; energy efficiency; system reliability;

D O I：

10.1109/ICCD.2017.105

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the performance and system reliability constraints that are key impediments to VLV. The associated trade-offs across power, performance and reliability are helpful in inferring the optimal operational voltage-frequency point. This work was performed under the auspices of an ongoing DARPA program (named PERFECT) that is focused on maximizing system-level energy efficiency.

引用

页码：601 / 604

页数：4

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