High-MDSI: A high-level signal integrity fault test pattern generation method for interconnects

被引：3
|
作者：
Chun, Sunghoon [1 ]
Kim, Yongjoon [1 ]
Kang, Sungho [1 ]
机构：
[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul 120749, South Korea
来源：
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM | 2007年
关键词：
signal integrity; interconnect test; RLC interconnect model; fault modeling;
D O I：
10.1109/ATS.2007.58
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.
引用
收藏
页码：115 / 118
页数：4
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