Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

被引：11

作者：

Allen, Gregory ^{[1
]}

Edmonds, Larry D. ^{[1
]}

Swift, Gary ^{[2
]}

Carmichael, Carl ^{[2
]}

Tseng, Chen Wei ^{[2
]}

Heldt, Kevin ^{[3
]}

Anderson, Scott Arlo ^{[3
]}

Coe, Michael ^{[3
]}

机构：

[1] CALTECH, Jet Prop Lab, Pasadena, CA 91109 USA

[2] Xilinx Inc, San Jose, CA USA

[3] SEAKR Engn Inc, Centennial, CO 80111 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2011年 / 58卷 / 03期

关键词：

Error rate calculation; field programmable gate array; single event upset; triple modular redundancy;

D O I：

10.1109/TNS.2011.2105282

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilinx Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

引用

页码：1040 / 1046

页数：7

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