Area-Efficent Power Clamp Circuit Using gate-coupled structure for Smart Power ICs

被引：0

作者：

Kim, Dong-Jun ^{[1
]}

Park, Ju-Ho ^{[1
]}

Park, Sang-Gyu ^{[1
]}

机构：

[1] Hanyang Univ, Div Elect & Comp Engn, Seoul 133791, South Korea

来源：

ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 | 2008年

关键词：

electrostatic discharge (ESD); gate-coupled structure; power clamp circui; smart power technology;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The performance of the proposed ESD power clamp was successfully verified in a 0.35 mu m 60V BCD (Bipolar CMOS DMOS) process by TLP (Transmission Line Pulse) measurements.

引用

页码：429 / 430

页数：2

共 7 条

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