Design and Implementation of Multimode CFAR Processor

Over the past few decades different Constant False Alarm Rate (CFAR) algorithms have been developed to effectively deal with the various types of backgrounds (noise/stationary clutter) that are encountered. However, any single algorithm is likely to be inadequate in a dynamically changing environment. A solution for this problem is presented in this paper which is to design partially reconfigurable hardware architecture for CFAR signal processor which can switch between multiple CFAR algorithms. Novel hardware architectures for the computationally extensive algorithms Cell Average (CA), Ordered Statistics (OS) and Trimmed Mean (TM) CFAR has been developed which are efficient and simple, with low developmental cost. The partially reconfigurable (PR) CFAR processor has been ported on a Virtex-6SX240t FPGA using the ML605 board. The processor was tested on moving target indicator (MTI) processed data from a ServiceableTA-10K radar.