Energy-efficient;
High linearity;
Trade-off;
SAR ADC;
CMOS;
D O I:
10.1007/s10470-015-0651-7
中图分类号:
TP3 [计算技术、计算机技术];
学科分类号:
0812 ;
摘要:
A high linearity energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Monotonic switching scheme and split-capacitor technique are combined. This scheme has no reset energy consumption, and achieves purely 98.05 % less switching energy and 75 % reduction of the total capacitance over the conventional architecture. Moreover, the proposed scheme also improves the linearity of SAR ADC. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.116LSB and 0.083LSB, respectively. The proposed scheme achieves a well trade-off between energy and linearity.