Computing in 3D

被引:0
作者
Franzon, Paul [1 ]
Rotenberg, Eric [1 ]
Tuck, James [1 ]
Davis, W. Rhett [1 ]
Zhou, Huiyang [1 ]
Schabel, Joshua [1 ]
Zhang, Zhenquian [1 ]
Dwiel, J. Brandon [1 ]
Forbes, Elliott [1 ]
JoonmooHuh [1 ]
Lipa, Steve [1 ]
机构
[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA
来源
2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2015年
关键词
3DIC; TSVs; CPUs; Processors;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
3D technologies offer significant potential to improve total performance and performance per unit of power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create sophisticated logic on logic solutions that promise further increases in performance/power beyond those attributable to memory interfaces alone. These include heterogenous integration for computing and exploitation of the high amounts of 3D interconnect available to reduce total interconnect power. Challenges include access for prototype quantities and the design of sophisticated static and dynamic thermal management methods and technologies, as well as test.
引用
收藏
页数:6
相关论文
共 50 条
[31]   Investigation of the Dynamics of Liquid Cooling of 3D ICs [J].
Islam, Sakib ;
Motaleb, Ibrahim Abdel .
2019 8TH INTERNATIONAL SYMPOSIUM ON NEXT GENERATION ELECTRONICS (ISNE), 2019,
[32]   Cost Model for Monolithic 3D Integrated Circuits [J].
Gitlin, Daniel ;
Vinet, Maud ;
Clermidy, Fabien .
2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2016,
[33]   Reduction of Temperature Rise in 3D IC Routing [J].
Pandiaraj, K. ;
Sivakumar, P. ;
Geetharamani, N. .
2017 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, INSTRUMENTATION AND COMMUNICATION ENGINEERING (ICEICE), 2017,
[34]   A review of thermal performance of 3D stacked chips [J].
Wang, Zhiqiang ;
Dong, Rui ;
Ye, Rihong ;
Singh, Salvinder Singh Karam ;
Wu, Shaofeng ;
Chen, Chenxu .
INTERNATIONAL JOURNAL OF HEAT AND MASS TRANSFER, 2024, 235
[35]   An Error Tolerance Scheme for 3D CMOS Imagers [J].
Chang, Hsiu-Ming ;
Huang, Jiun-Lang ;
Kwai, Ding-Ming ;
Cheng, Kwang-Ting ;
Wu, Cheng-Wen .
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, :917-922
[36]   A Force Directed Partitioning Algorithm for 3D Floorplanning [J].
Lyu, Linquan ;
Yoshimura, Takeshi .
2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, :718-721
[37]   Modeling and Analysis of Transient Heat for 3D IC [J].
Chatterjee, Subhajit ;
Roy, Surajit Kr. ;
Giri, Chandan ;
Rahaman, Hafizur .
VLSI DESIGN AND TEST, 2017, 711 :365-375
[38]   Fault-Tolerant 3D Clock Network [J].
Lung, Chiao-Ling ;
Su, Yu-Shih ;
Huang, Shih-Hsiu ;
Shi, Yiyu ;
Chang, Shih-Chieh .
PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, :645-651
[39]   3D Integration Technologies for MEMS/IC Systems [J].
Ramm, Peter ;
Klumpp, Armin ;
Weber, Josef .
PROCEEDINGS OF THE 2009 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2009, :138-141
[40]   Adaptive Clock Distribution for 3D Integrated Circuits [J].
Chen, Xi ;
Davis, W. Rhett ;
Franzon, Paul D. .
2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, :91-94