An all-digital DFT scheme for testing catastrophic faults in PLLs

被引：27
作者：
Azaïs, F
Bertrand, Y
Renovell, M
Ivanov, A
Tabatabaei, S
机构：
[1] Univ Montpellier, CNRS, Microelect Dept, LIRMM, F-34392 Montpellier, France
[2] Univ British Columbia, Dept Elect & Comp Engn, Vancouver, BC V5Z 1M9, Canada
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2003年 / 20卷 / 01期
基金：
加拿大自然科学与工程研究理事会;
关键词：
D O I：
10.1109/MDT.2003.1173054
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Traditional functional testing of mixed-signal ICs is slow and requires costly, dedicated test equipment. The authors update the standard PLL architecture to allow simple digital testing. The all-digital strategy yields catastrophic fault coverage as high as that of the classical functional test, plus it is fast, extremely simple to implement and requires only standard digital test equipment.
引用
收藏
页码：60 / 67
页数：8
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