Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification

被引：5

作者：

Im, Jaekyung ^{[1
]}

Kang, Seokhyeong ^{[1
]}

机构：

[1] POSTECH, Dept Elect Engn, Pohang, South Korea

来源：

18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021) | 2021年

关键词：

VLSI; RTL; hardware design language;

D O I：

10.1109/ISOCC53507.2021.9614007

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Chisel is a hardware design method that uses Scala programming language, and exploits many useful features of Scala like object-oriented programming and functional programming. By comparing two equivalent RISC-V core designs, one implemented using each hand-written Verilog code and one using Chisel, this paper compares manual Verilog coding and Chisel coding. The comparison metrics are source-code density, area of synthesized hardware, and RTL simulation run-time. As a result, Chisel is proved to be more productive than Verilog.

引用

页码：59 / 60

页数：2