A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth

A new combinatorial impairment-compensation digital predistorter (DPD) for a sub-GHz IEEE 802.11af-WLAN CMOS transmitter (TX) is proposed. For the TX to cover a 10x-wide bandwidth, the DPD implements a modified dynamic deviation reduction (DDR)-based Volterra series to jointly nullify the frequency-dependent I/Q imbalance, counter-intermodulation (CIM) of mixers, and nonlinearities of power amplifier (PA) with memory effect. The interactions of those impairments are firstly analyzed using two Volterra series. After applying the tandem properties of Volterra series, interactions of all impairments can be described in one Volterra series by bonding those impairments in parallel. Coefficients of the DPD are extracted with the Least-Square (LS) estimator, achieving lower running complexity than the existing DPDs, which were developed to handle the PA nonlinearities only. Verifications are based on both system-level simulations and silicon measurements of a 65-nm CMOS TX prototype. When the TX delivers a 6-MHz bandwidth, 2048-point, 64-QAM OFDM signal at > +10 dBm output power, the measured EVM is <3.7% and adjacent channel leakage ratio (ACLR) is < -40.2 dBc under individual DPD applied at each RF. A novel one-shot calibration for reuse in the entire TV-band is demonstrated also, showing EVM <4.2% and ACLR < -39.8 dBc.