Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

被引：5

作者：

Cortes, I. ^{[1
]}

Toulon, G. ^{[2
,3
]}

Morancho, F. ^{[2
,3
]}

Flores, D. ^{[1
]}

Hugonnard-Bruyere, E. ^{[4
]}

Villard, B. ^{[4
]}

机构：

[1] Inst Microelect Barcelona IMB CNM CSIC, Barcelona 08193, Spain

[2] CNRS, LAAS, F-31077 Toulouse, France

[3] Univ Toulouse 1, UPS, INSA, ISAE,LAAS, F-31077 Toulouse, France

[4] ATMEL Rousset, Zone Ind, F-13106 Rousset, France

来源：

SOLID-STATE ELECTRONICS | 2012年 / 70卷

关键词：

Thin-SOI technology; CMOS; LDMOS; RESURF; P-channel; NBL; TCAD; DESIGN;

D O I：

10.1016/j.sse.2011.11.012

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper analyses the experimental results of voltage capability (V-BR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 mu m SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/V-BR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors. (C) 2011 Elsevier Ltd. All rights reserved.

引用

页码：8 / 13

页数：6

共 9 条

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