Efficient low-latency RC4 architecture designs for IEEE 802.11i WEP/TKIP

In this paper, novel low-latency RC4 implementations with cell-based VLSI design flow are proposed for 802.11i WEP/TKIP. The RC4 stream cipher is used in the security protocol WEP in 802.11b wireless network, and is also used in the TKIP of wireless network 802.11i cryptography. The major process of RC4 algorithm is to shuffle the memory continuously. For quick memory shuffling, we investigate two different memory shuffling architectures to design the RC4. By using single-port 128x16 memory design, this architecture reduces 25% shuffling latency, compared with the conventional single-port 256x8 architecture. By using dual-port 256x8 memory design, this architecture achieves less latency and less power consumption at the same time. Both of the proposed architectures can reduce much latency in comparison with the conventional single-port 256x8 memory design.