Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor

Multiplier is one of the most important arithmetic blocks in computer arithmetic units, which affects the performance of the whole system. Improving efficiency and reducing power consumption can be achieved at the cost of reducing the computation accuracy. One approach to design approximate multipliers is to use an approximate compressor. This paper proposes an approximate compressor to be exploited in a multiplier circuit. The proposed compressor consists of only one gate. According to the simulation results with 28-nm standard cell-based technology, the proposed approximate compressor improves by 62% compared to the fastest available work. Also, at equal delays, its power consumption and area improve by 52% and 61%, respectively, compared with the best existing design. Moreover, the results indicate that the proposed approximate compressor may provide up to 53%, 86%, and 57% improvements in power-delay product, energy-delay product, and area-delay product, respectively, compared to the most efficient design. Finally, the efficiency of the proposed multiplier is investigated in image applications. The results show that the efficiency of the proposed multiplier excels the existing approximate and accurate counterparts.