Variability Study of Ferroelectric Field-Effect Transistors Towards 7nm Technology Node

被引：24

作者：

Choe, Gihun ^{[1
]}

Yu, Shimeng ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30326 USA

来源：

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2021年 / 9卷

关键词：

FeFETs; Grain size; Threshold voltage; Logic gates; Silicon-on-insulator; Semiconductor process modeling; Iron; Ferroelectrics; process variations; polycrystalline phases; nonvolatile memory; IMPACT; FUTURE;

D O I：

10.1109/JEDS.2021.3100290

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The random variation sources have a significant influence on the performance of ferroelectric field-effect transistor (FeFET). In this work, comparative analysis on the process variation induced variability of FeFET towards a 7 nm technology node has been conducted, including different device structures from bulk to FDSOI and FinFET. The random ferroelectric/dielectric phase variation (PV), the metal work function variation (WFV) and the line-edge roughness (LER) effects are incorporated in TCAD simulations to quantitatively investigate their impacts on the threshold voltage variation. Especially, the Voronoi diagram is employed to realistically model the ferroelectric grain distributions and to accurately simulate the impact of PV on FeFET characteristics.

引用

页码：1131 / 1136

页数：6

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