Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder

被引：0

作者：

Gupta, AK ^{[1
]}

Nooshabadi, S ^{[1
]}

Montiel-Nelson, J ^{[1
]}

机构：

[1] Univ New S Wales, Sydney, NSW, Australia

来源：

VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 | 2005年 / 5837卷

关键词：

JPEG2000; Buffer Design; VLSI architecture; EBCOT block coder; Concurrent symbol Processing;

D O I：

10.1117/12.608585

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present the VLSI architecture for the buffer for tier-I of EBCOT encoder of JPEG2000. The buffer allows the integration of bit-plane coder and arithmetic coder module employing concurrent symbol processing technique. The buffer architecture is optimized by exploiting the natural image statistics to optimally choose the buffer length parameter. The overall architecture is implemented using Altera FPGA and experimental results show a savings of 59% in the hardware cost with minimal reduction in the overall throughput.

引用

页码：185 / 192

页数：8

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