Performance evaluation of an on-chip multi-threaded processor with cache memory managed by logical thread number

被引：0
作者：
Nakajo, H
Yamato, M
Kawahara, S
Kato, N
Sasada, K
Sato, M
Namiki, M
机构：
来源：
PDPTA'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS 1-4 | 2003年
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中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
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页码：1775 / 1781
页数：7
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