Fermi-level pinning in full metal/high-k/SiO2/Si stacks

被引：4

作者：

Huang, Anping ^{[1
]}

Zhang, Xinjiang ^{[1
]}

Li, Yue ^{[1
]}

Wang, Mei ^{[1
]}

Xiao, Zhisong ^{[1
]}

机构：

[1] Beihang Univ, Sch Phys, Beijing 100191, Peoples R China

来源：

JOURNAL OF APPLIED PHYSICS | 2017年 / 122卷 / 19期

基金：

中国国家自然科学基金;

关键词：

WORK-FUNCTION; METAL GATE; DEVICES; TECHNOLOGY; INTERFACES; FINFET;

D O I：

10.1063/1.5005570

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Fermi-level pinning (FLP) in full Metal/High-k/SiO2/Si stacks is investigated based on the improved electron state density (IESD) model. The SiO2 interlayer between the high-k layer and Si and the effects of the high-k/SiO2/Si interface on FLP are analyzed. The effective work function (EWF) is influenced by the density of states in high-k/SiO2/Si stacks with the exception of the effects of the electron state density in the metal gate. The IESD model provides physical insights and is a simple and convenient method to calculate the EWF of MOS devices with different types. (C) 2017 Author(s).

引用

页数：6

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[31] Monitoring of Fermi level variations at metal/high-k interfaces with in situ x-ray photoelectron spectroscopy [J].

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[33] Impact of sputter deposited TaN and TiN metal gates on ZrO2/Ge and ZrO2/Si high-k dielectric gate stacks [J].

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[34] Thermally unstable ruthenium oxide gate electrodes in Metal/High-k gate stacks [J].

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[40] Silicon-atom induced fermi-level pinning of fully silicided platinum gates on HfO2 dielectrics [J].

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Akiyama, K ;

Mise, N ;

Migita, S ;

Iwamoto, K ;

Yasuda, N ;

Tominaga, K ;

Ikeda, M ;

Satake, H ;

Nabatame, T ;

Toriumi, A .

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