RTL-level modeling of an 8B/10B encoder-decoder using SystemC

被引:0
作者
Aref, I. A. [1 ]
Ahmed, N. A. [1 ]
Rodriguez-Salazar, F. [1 ]
Elgaid, K. [1 ]
机构
[1] Univ Glasgow, Dept Elect & Elect Engn, Glasgow G12 8LT, Lanark, Scotland
来源
2008 IFIP INTERNATIONAL CONFERENCE ON WIRELESS AND OPTICAL COMMUNICATIONS NETWORKS | 2008年
关键词
SystemC; modeling; SoC; IP; pinout; RTL; 8B/10B; encoder; decoder;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an RTL-level model of an 8B/10B encoder/decoder block in SystemC. The use of 8B/10B coding is an important technique in the construction of high performance serial interfaces. These are particularly suitable for alleviating the I/O bottleneck of state of the art systems (which are pinout, rather than bandwidth limited). SystemC has been chosen because it provides a homogeneous design flow for complex designs (i.e. SoC and IP based design), where system modeling at the early stages of the design becomes increasingly important.
引用
收藏
页码:80 / 83
页数:4
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