Current Degradation and Delay Analysis of Series-Connected Circuits Based on Novel TFET Design

In this paper, for the first time, we investigate the circuit current degradation behavior in series-connected structures based on conventional Tunnel FET (TFET) and our proposed Multi-Finger Schottky-barrier TFET (MFSB-TFET). Due to the suppressed super-linear onset behavior in the output characteristics of MFSI3-TFET, the current degradation issue in serious-connected structure for conventional TFET can be much alleviated, Correspondingly, the circuit delay ratio defined as the pull down delay of N-input NAND over the pull down delay of inverter is investigated to character the impact of this issue on circuits. The simulation results reveals that MFSB-TFET has a similar behavior to MOSFET in the series-connected structures while conventional TFET shows much more delay sacrifice.