Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

被引：360

作者：

Stojanovic, V ^{[1
]}

Oklobdzija, VG

机构：

[1] Univ Belgrade, Fac Elect Engn, YU-11001 Belgrade, Yugoslavia

[2] Integrat Corp, Berkeley, CA 94708 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 04期

关键词：

D O I：

10.1109/4.753687

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

引用

页码：536 / 548

页数：13

共 16 条

[1] New single-clock CMOS latches and flip-flops with improved speed and power savings - Comment [J].

Blair, GM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (10) :1610-1611

[2] Circuit techniques in a 266-MHz MMX-enabled processor [J].

Draper, D ;

Crowley, M ;

Holst, J ;

Favor, G ;

Schoy, A ;

Trull, J ;

BenMeir, A ;

Khanna, R ;

Wendell, D ;

Krishna, R ;

Nolan, J ;

Mallick, D ;

Partovi, H ;

Roberts, M ;

Johnson, M ;

Lee, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (11) :1650-1664

[3]

FISHER GJ, 1988, IEEE T COMPUTER AIDE, V7

[4] A 2.2-W, 80-MHZ SUPERSCALAR RISC MICROPROCESSOR [J].

GEROSA, G ;

GARY, S ;

DIETZ, C ;

PHAM, D ;

HOOVER, K ;

ALVAREZ, J ;

SANCHEZ, H ;

IPPOLITO, P ;

NGO, T ;

LITCH, S ;

ENO, J ;

GOLAB, J ;

VANDERSCHAAF, N ;

KAHLE, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1440-1454

[5] A 600MHz superscalar RISC microprocessor with out-of-order execution [J].

Gieseke, BA ;

Allmon, RL ;

Bailey, DW ;

Benschneider, BJ ;

Britton, SM ;

Clouser, JD ;

Fair, HR ;

Farrell, JA ;

Gowan, MK ;

Houghton, CL ;

Keller, JB ;

Lee, TH ;

Leibholz, DL ;

Lowell, SC ;

Matson, MD ;

Matthew, RJ ;

Peng, V ;

Quinn, MD ;

Priore, DA ;

Smith, MJ ;

Wilcox, KE .

1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 :176-177

[6]

Klass F., 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), P108, DOI 10.1109/VLSIC.1998.688018

[7]

KO U, 1996, ISLPED AUG

[8] A 200-MHZ 13-MM(2) 2-D DCT MACROCELL USING SENSE-AMPLIFYING PIPELINE FLIP-FLOP SCHEME [J].

MATSUI, M ;

HARA, H ;

UETANI, Y ;

KIM, LS ;

NAGAMATSU, T ;

WATANABE, Y ;

MATSUDA, K ;

SAKURAI, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1482-1490

[9] A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor [J].

Montanaro, J ;

Witek, RT ;

Anne, K ;

Black, AJ ;

Cooper, EM ;

Dobberpuhl, DW ;

Donahue, PM ;

Eno, J ;

Hoeppner, GW ;

Kruckemyer, D ;

Lee, TH ;

Lin, PCM ;

Madden, L ;

Murray, D ;

Pearce, MH ;

Santhanam, S ;

Snyder, KJ ;

Stephany, R ;

Thierauf, SC .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1703-1714

[10] Flow through latch and edge-triggered flip-flop hybrid elements [J].

Partovi, H ;

Burd, R ;

Salim, U ;

Weber, F ;

DiGregorio, L ;

Draper, D .

1996 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 1996, 39 :138-139

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