Systematic Analysis of Interleaved Digital-to-Analog Converters

被引：46

作者：

Balasubramanian, S.

Creech, G. ^{[2
]}

Wilson, J. ^{[3
]}

Yoder, S. M. ^{[1
]}

McCue, J. J. ^{[1
]}

Verhelst, M. ^{[4
]}

Khalil, W. ^{[1
]}

机构：

[1] Ohio State Univ, Dept Elect & Comp Engn, Columbus, OH 43210 USA

[2] USAF, Adv Sensor Components Branch, Res Lab, Hanscom Afb, MA 01731 USA

[3] USA, Res Lab, Washington, DC 20314 USA

[4] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Heverlee, Belgium

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2011年 / 58卷 / 12期

基金：

美国国家科学基金会;

关键词：

DDRF-DAC; digital-to-analog converters (DACs); interleaving; reconstruction;

D O I：

10.1109/TCSII.2011.2172526

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N-parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.

引用

页码：882 / 886

页数：5

共 12 条

[1]

[Anonymous], P IEEE INT C ULTR

[2] Direct digital-to-RF digital-to-analogue converter using image replica and nonlinearity cancelling architecture [J].