A Highly Linear Dual-Band Mixed-Mode Polar Power Amplifier in CMOS with An Ultra-Compact Output Network

This paper presents a highly linear dual-band mixed-mode polar power amplifier (PA) fully integrated in a standard 65 nm bulk CMOS process. An ultra-compact single-transformer-based passive network provides optimum load impedance transformations simultaneously at two operating frequencies, parallel power combining, and even-harmonic rejection without any tuning elements or band selection switches. The mixed-mode PA architecture leverages both digital and analog techniques to dynamically suppress the AM-AM and AM-PM distortions, achieving high linearity. As a proof-of-concept design, a dual-band mixed-mode polar PA is implemented in a standard 65 nm CMOS process. It demonstrates a peak output power of + 28.1 dBm/+26.0 dBm with a PA drain efficiency of 40.7%/27.0% at 2.6 GHz/4.5 GHz, respectively. The measured 2nd harmonic rejection for the 2.35 GHz signal is 36 dB. Modulation tests with 8 MSym/s 256-QAM signals achieve the measured rms EVM of 1.53%/1.87% with the average output power of + 20.37 dBm/+ 18.53 dBm and the PA drain efficiency of 16.26%/13.42% at 2.35 GHz/4.7 GHz, demonstrating a highly linear and efficient dual-band mixed-mode polar PA.