Concurrent analysis of signal-power integrity and EMC for high-speed signaling systems

被引:0
|
作者
Chan, Edward K. [1 ]
Lai, Mauro [1 ]
Choi, Myoung Joon [1 ]
Ryu, Woong Hwari [1 ]
机构
[1] Intel Corp, Santa Clara, CA 95051 USA
关键词
codesign; signal integrity; power integrity; EMC; power noise coupling; signal trace resonance;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A robust co-analysis approach for signal integrity, power integrity, and electromagnetic compatibility is successfully established and demonstrated through the investigation of several signal referencing configurations in Double Data Rate (DDR) memory systems. The characterization of power noise coupling into signal channels for two configurations is presented. In addition, a new metric that quantifies the entire signaling system combining simultaneous switching noise and crosstalk is detailed. Finally, the radiated emissions from the power planes in the signalling system are reduced through the proper placement of decoupling capacitors.
引用
收藏
页码:77 / 84
页数:8
相关论文
共 50 条
  • [1] Ensuring Signal and Power Integrity for High-Speed Digital Systems An EMC Perspective
    Schuster, Christian
    2015 IEEE 5TH INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - BERLIN (ICCE-BERLIN), 2015, : 205 - 207
  • [2] SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation
    Dong, Xiao
    Sun, Songyu
    Jiang, Yangfan
    Hu, Jingtong
    Gao, Dawei
    Zhuo, Cheng
    29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024, 2024, : 625 - 630
  • [3] Signal integrity and EMC in high-speed electronic package integration
    Li, E. P.
    2007 ASIA-PACIFIC CONFERENCE ON APPLIED ELECTROMAGNETICS, PROCEEDINGS, 2007, : 7 - 10
  • [4] Controllable parameters identification for high speed channel through signal-power integrity combined analysis
    Choi, Myoung Joon
    Pandit, Vishram S.
    Ryu, Woong Hwan
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 658 - +
  • [5] Signal and Power Integrity Analysis for the Novel Power Plane of EBG Structure in High-Speed Mixed Signal Systems
    Zhu, Hao-Ran
    Mao, Jun-Fa
    Li, Jian-Jie
    2013 IEEE INTERNATIONAL WIRELESS SYMPOSIUM (IWS), 2013,
  • [6] Signal and Power Integrity Analysis of High-Speed Links with Silicon Interposer
    Beyene, Wendemagegnehu
    Juneja, Nitin
    Hahm, Yeon-Chang
    Kollipara, Ravi
    Kim, Joohee
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1708 - 1715
  • [7] Statistical signal integrity analysis and diagnosis methodology for high-speed systems
    Matoglu, E
    Pham, N
    de Araujo, DN
    Cases, M
    Swaminathan, M
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2004, 27 (04): : 611 - 629
  • [8] High-Speed Signal Integrity Design for HDCA Systems
    Kwon, Wonok
    Kim, Young Woo
    2018 INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGY CONVERGENCE (ICTC), 2018, : 1267 - 1269
  • [9] Signal-Power Integrity Co-Simulations of High Speed Systems via Chip-Package-PCB Co-Analysis Methodology
    Wen Jiwei
    Jing Weiping
    2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2013, : 485 - 491
  • [10] Power and Signal Integrity Analysis of High-speed Mixed-signal Backplane Based on VPX
    Meng Hua
    Niu Minxi
    Tan Anju
    Miao Jianghong
    2018 IEEE SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL INTEGRITY AND POWER INTEGRITY (EMC, SI & PI), 2018, : 577 - 581