Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits

被引：21

作者：

Nagasawa, S ^{[1
]}

Hinode, K ^{[1
]}

Sugita, M ^{[1
]}

Satoh, T ^{[1
]}

Akaike, H ^{[1
]}

Kitagawa, Y ^{[1
]}

Hidaka, M ^{[1
]}

机构：

[1] ISTEC, Supercond Res Lab, Tsukuba, Ibaraki 3058501, Japan

来源：

SUPERCONDUCTOR SCIENCE & TECHNOLOGY | 2003年 / 16卷 / 12期

关键词：

D O I：

10.1088/0953-2048/16/12/036

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We have been developing a 10 kA cm(-2) Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.

引用

页码：1483 / 1486

页数：4

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