Physics of deep submicron CMOS VLSI

被引:0
|
作者
Buss, DD [1 ]
机构
[1] Texas Instruments Inc, Dallas, TX 75243 USA
来源
关键词
D O I
暂无
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
The Integrated Circuit (IC) was invented in 1958, and modem CMOS was invented in 1980. The semiconductor physics that underlies the IC was discovered in the early part of the past century, and, by the early 60's, it was simplified and codified such that it could be used by engineers to design transistors of ever shrinking size and increasing performance. However, in recent years, the "Electrical Engineering Physics" of the 60's is becoming increasingly inadequate. Empirical corrections are being made to allow for quantum and non-equilibrium Boltzmann transport effects. Moreover, as features in CMOS transistors reach atomic dimensions, continuum physics is no longer adequate, and devices must be designed increasingly, at the atomic level. As transistors approach the end of scaling, the physics to design them will become increasingly complex, and Electrical Engineering Physics will no longer suffice.
引用
收藏
页码:1591 / 1594
页数:4
相关论文
共 50 条
  • [1] Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits
    Zjajo, Amir
    van der Meijs, Nick
    van Leuken, Rene
    JOURNAL OF LOW POWER ELECTRONICS, 2013, 9 (04) : 403 - 413
  • [2] SUBMICRON CMOS/SOS PROCESS FOR VLSI.
    Maddox, Roy L.
    Casey Nancy
    Sallee, Carol
    Kinoshita, Frieda
    Imerson, Rob
    Whitcomb, Gene
    1600, (25):
  • [3] A Novel Approach for Leakage Power Reduction in Deep Submicron Technologies in CMOS VLSI Circuits
    Dadoria, Ajay Kumar
    Khare, Kavita
    Singh, R. P.
    2015 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATION AND CONTROL (IC4), 2015,
  • [4] Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
    IEEE
    不详
    不详
    不详
    IEEE Trans Semicond Manuf, 4 (396-402):
  • [5] Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
    Nardi, A
    Neviani, A
    Zanoni, E
    Quarantelli, M
    Guardiani, C
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1999, 12 (04) : 396 - 402
  • [6] GDNMOS Design for ESD protection in Submicron CMOS VLSI
    Li Zhiguo
    Yue Suge
    Sun Yongshu
    2009 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIMEASIA 2009), 2009, : 432 - 435
  • [7] CONTAMINATION CONTROL FOR A SUBMICRON CMOS VLSI ULSI FACTORY
    WORKMAN, WL
    9TH INTERNATIONAL SYMPOSIUM ON CONTAMINATION CONTROL : EXPLORING WORLD PARTNERSHIPS IN TECHNOLOGY, 1988, : 104 - 109
  • [8] Datapath allocation algorithm for deep submicron VLSI
    Wang, L
    Wei, SJ
    2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4, 2002, : 1411 - 1414
  • [9] Submicron CMOS transient test structure for low power VLSI
    Lee, M
    1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, : 759 - 762
  • [10] SoC integration in deep submicron CMOS
    Rickert, P
    Haroun, B
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 653 - 656