Surface Potential Based Model of Ultra-Thin Fully Depleted SOI MOSFET for IC Simulations

被引：0
作者：
Rozeau, Olivier
Jaud, Marie-Anne
Poiroux, Thierry
Benosman, Mohamed
机构：
来源：
2011 IEEE INTERNATIONAL SOI CONFERENCE | 2011年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页数：22
相关论文
共 50 条
[11]   Diffusion-drift model of fully depleted SOI MOSFET [J].
Zebrev, G. I. ;
Gorbunov, M. S. .
2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2006, :545-+
[12]   Buried-oxide charge trapping induced performance degradation in fully-depleted ultra-thin SOI p-MOSFET's [J].
Wei, HF ;
Chung, JE ;
Annamalai, NK .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (08) :1200-1205
[13]   A specific floating-body effect in fully depleted SOI MOSFETs with ultra-thin gate oxide [J].
Cassé, M ;
Prétet, J ;
Cristoloveanu, S ;
Poiroux, T ;
Raynaud, C ;
Reimbold, G .
MICROELECTRONIC ENGINEERING, 2004, 72 (1-4) :352-356
[14]   Comprehensive study of the statistical variability in a 22 nm fully depleted ultra-thin-body SOI MOSFET [J].
Zain, Anis Suhaila Mohd ;
Markov, Stanislav ;
Cheng, Binjie ;
Asenov, Asen .
SOLID-STATE ELECTRONICS, 2013, 90 :51-55
[15]   Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability [J].
Schwarzenbach, Walter ;
Nguyen, Bich-Yen ;
Allibert, Frederic ;
Girard, Christophe ;
Maleville, Christophe .
SOLID-STATE ELECTRONICS, 2016, 117 :2-9
[16]   An analytical continuous model of a fully depleted SOI MOSFET applicable for CAD [J].
Jurczak, M ;
Jakubowski, A .
1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, :351-354
[17]   Completely surface-potential-based compact model of the-fully depleted SOI-MOSFET including short-channel effects [J].
Sadachika, Norio ;
Kitamaru, Daisuke ;
Uetsuji, Yasuhito ;
Navarro, Dondee ;
Yusoff, Marmee Mohd ;
Ezaki, Tatsuya ;
Mattausch, Hans Juergen ;
Miura-Mattausch, Mitiko .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (09) :2017-2024
[18]   Device footprint scaling for ultra thin body fully depleted SOI [J].
Deng, Jie ;
Kim, Keunwoo ;
Chuang, Ching-Te ;
Wong, H. -S Philip .
ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2007, :145-+
[19]   Hot-carrier effect in ultra-thin-film (UTF) fully-depleted SOI MOSFET's [J].
Yu, B ;
Ma, ZJ ;
Zhang, G ;
Ha, CM .
1996 54TH ANNUAL DEVICE RESEARCH CONFERENCE DIGEST, 1996, :22-23
[20]   PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations [J].
Wu, W. ;
Li, X. ;
Gildenblat, G. ;
Workman, G. O. ;
Veeraraghavan, S. ;
McAndrew, C. C. ;
van Langevelde, R. ;
Smit, G. D. J. ;
Scholten, A. J. ;
Klaassen, D. B. M. ;
Watts, J. .
SOLID-STATE ELECTRONICS, 2009, 53 (01) :18-29
12345