Rotary pipeline processors

被引：3
作者：
Moore, S
Robinson, P
Wilcox, S
机构：
[1] Computer Laboratory, University of Cambridge, New Museums Site, Cambridge CB2 3QG, Pembroke Street
来源：
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 1996年 / 143卷 / 05期
关键词：
rotary pipeline processors; superscalar processors; self-timed logic;
D O I：
10.1049/ip-cdt:19960657
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The rotary pipeline processor is a new architecture for superscalar computing. It is based on a simple and regular pipeline structure which can support several ALUs for efficient dispatching of multiple instructions. Register values flow around a rotary pipeline, constrained by local data dependencies. During normal operation the control circuits are not on the critical path and performance is only limited by data rates. The architecture is particularly well suited to implementation using self-timed logic.
引用
收藏
页码：259 / 265
页数：7
相关论文
共 17 条
[1]  
*ARM, 1995, ARM7TDMI ADV RISC MA
[2]   AN EFFICIENT IMPLEMENTATION OF BOOLEAN FUNCTIONS AS SELF-TIMED CIRCUITS [J].
DAVID, I ;
GINOSAR, R ;
YOELI, M .
IEEE TRANSACTIONS ON COMPUTERS, 1992, 41 (01) :2-11
[3]  
FURBER SB, 1994, PR IEEE COMP DESIGN, P217, DOI 10.1109/ICCD.1994.331891
[4]  
Furber SB., 1989, VLSI RISC ARCHITECTU
[5]   ASYNCHRONOUS DESIGN METHODOLOGIES - AN OVERVIEW [J].
HAUCK, S .
PROCEEDINGS OF THE IEEE, 1995, 83 (01) :69-93
[6]  
HENNESSY JL, 1996, COMPUTER ARCHITECTUR, pA5
[7]  
MILLER RE, 1965, SWITCHING THEORY, V2, pCH10
[8]  
Paver N.C, 1994, THESIS U MANCHESTER
[9]  
SEITZ CL, 1992, INTRO VLSI SYSTEMS
[10]  
Sites R.L., 1992, ALPHA ARCHITECTURE R
12