Characterization and Implementation of Nonlinear Logic Cell Models for Analog Circuit Simulation

被引：0

作者：

Knoth, Christoph ^{[1
]}

Kleeberger, Veit B. ^{[1
]}

Nordholz, Petra ^{[2
]}

Schlichtmann, Ulf ^{[1
]}

机构：

[1] Tech Univ Munich, Inst Elect Design Automat, D-8000 Munich, Germany

[2] Infineon Technol AG, Neuherberg, Germany

来源：

PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009) | 2009年

关键词：

CMOS; gate modeling; simulation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

During back-end verification of digital circuits, analog circuit simulation is an indispensable, but time consuming, process. To reduce simulation time, current source models (CSMs) have been proposed to replace transistor netlists of logic cells. In this paper, physically motivated requirements for accurate CSMs are derived. By employing the topological information of the netlist, very short characterization times and high accuracy are achieved. Implemented as compiled models in a standard SPICE simulator, CSMs reduce simulation times by two orders of magnitude.

引用

页码：17 / +

页数：2

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