SCR-based ESD protection for high bandwith DRAMs

A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and C(in). (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5kV and MM-500V stress. The input capacitance, C(in), was measured to be 1.5pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277ps (55.3% of UI) in DDR3 interface at 2Gbps operation due to the C(in) reduction effect.