EFFECTS OF GATE TUNNELING CURRENT ON THE STATIC CHARACTERISTICS OF CMOS CIRCUITS

With the scaling of MOS devices, gate tunneling current increases in exponential with thinner gate oxides, and the static standby power consumption of CMOS circuits is severely affected by the presence of gate tunneling currents. To illustrate the impacts, in this paper, a simpler gate tunneling current theory model by a double integral approach in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness is presented. The simulation results well agree with the theory model proposed in BSIM4. The characteristics of current source inverter composed of ultra-thin gate oxide MOS devices are also studied in detail to analyze its behavior and predict the trends of power dissipated with scaled technology nodes in the effects of gate tunneling current.