A Ferroelectric FET-Based Processing-in-Memory Architecture for DNN Acceleration

被引：56

作者：

Long, Yun ^{[1
]}

Kim, Daehyun ^{[1
]}

Lee, Edward ^{[1
]}

Saha, Priyabrata ^{[1
]}

Mudassar, Burhan Ahmad ^{[1
]}

She, Xueyuan ^{[1
]}

Khan, Asif Islam ^{[1
]}

Mukhopadhyay, Saibal ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS | 2019年 / 5卷 / 02期

基金：

美国国家科学基金会;

关键词：

Virtual machine monitors; Engines; Clocks; Transistors; Logic gates; Computer architecture; Random access memory; Deep neural network (DNN); ferroelectric FET (FeFET); processing-in-memory (PIM);

D O I：

10.1109/JXCDC.2019.2923745

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a ferroelectric FET (FeFET)-based processing-in-memory (PIM) architecture to accelerate the inference of deep neural networks (DNNs). We propose a digital in-memory vector-matrix multiplication (VMM) engine design utilizing the FeFET crossbar to enable bit-parallel computation and eliminate analog-to-digital conversion in prior mixed-signal PIM designs. A dedicated hierarchical network-on-chip (H-NoC) is developed for input broadcasting and on-the-fly partial results processing, reducing the data transmission volume and latency. Simulations in 28-nm CMOS technology show 115xand 6.3xhigher computing efficiency (GOPs/W) over desktop GPU (NvidiaGTX1080Ti) and resistive random access memory (ReRAM)-based design, respectively.

引用

页码：113 / 122

页数：10

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