FPGA-based Personal Authentication Using Fingerprints

被引:16
作者
Fons, Mariano [1 ]
Fons, Francisco [1 ]
Canto, Enrique [1 ]
Lopez, Mariano [2 ]
机构
[1] Univ Rovira & Virgili, Dept Engn Elect Elect & Automat, Tarragona, Spain
[2] Univ Politecn Cataluna, Dept Elect Engn, Vilanova I La Geltru, Spain
来源
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2012年 / 66卷 / 02期
关键词
Biometrics; Field programmable gate array; Flexible hardware; Hardware-software co-design; Real-time embedded system; Run-time reconfigurable computing;
D O I
10.1007/s11265-011-0629-3
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.
引用
收藏
页码:153 / 189
页数:37
相关论文
共 49 条
[11]  
[Anonymous], SUPR SFM SER FING MO
[12]  
[Anonymous], 2009, HDB FINGERPRINT RECO
[13]  
[Anonymous], 3M COGENT SECURASIC
[14]  
[Anonymous], AUTHENTEC TCD50D DIG
[15]  
[Anonymous], FINGERPRINT CARDS FP
[16]  
Baldisserra D, 2006, LECT NOTES COMPUT SC, V3832, P265
[17]  
Barrenechea M, 2009, LECT NOTES ELECTR EN, V38, P247
[18]   Dynamic and partial FPGA exploitation [J].
Becker, Juergen ;
Huebner, Michael ;
Hettich, Gerhard ;
Constapel, Rainer ;
Eisenmann, Joachim ;
Luka, Juergen .
PROCEEDINGS OF THE IEEE, 2007, 95 (02) :438-452
[19]  
Chen HH, 2010, INT CONF SIGN PROCES, P549, DOI 10.1109/ICOSP.2010.5655032
[20]   Fingerprint enhancement with dyadic scale-space [J].
Cheng, JG ;
Tian, H .
PATTERN RECOGNITION LETTERS, 2004, 25 (11) :1273-1284