共 50 条
- [41] 3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (02): : 221 - 228
- [42] Modeling and Analysis of Coupling between TSVs, Metal, and RDL interconnects in TSV-based 3D IC with Silicon Interposer 2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 702 - +
- [43] Assembly Process and Reliability Assessment of TSV/RDL/IPD Interposer with Multi-Chip-Stacking for 3D IC Integration SiP 2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 548 - 554
- [45] Thermal management of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC) IEICE ELECTRONICS EXPRESS, 2016, 13 (11):
- [46] Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2022, 12 (06): : 956 - 963
- [47] FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System 2023 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS, COOL CHIPS, 2023,
- [48] Through Silicon Via(TSV) Defect/Pinhole Self Test Circuit for 3D-IC 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 170 - 177
- [49] Fault Isolation of Short Defect in Through Silicon Via (TSV) based 3D-IC 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
- [50] 3D Packaging of Embedded Opto-electronic Die and CMOS IC Based on Wet Etched Silicon Interposer 2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 551 - 556