共 10 条
- [2] A wafer-scale 3-D circuit integration technology [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (10) : 2507 - 2516
- [4] BONDING OF SILICON-WAFERS FOR SILICON-ON-INSULATOR [J]. JOURNAL OF APPLIED PHYSICS, 1988, 64 (10) : 4943 - 4950
- [5] Progress of 3D integration technologies and 3D interconnects [J]. PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2007, : 213 - 215
- [8] Tong Q.-Y., 2002, SILICON WAFER BONDIN, P13
- [10] Young H. D., 2008, U PHYS, P820