Novel SONOS-type nonvolatile memory device with stacked tunneling and charge-trapping layers

被引:0
作者
Tsai, Ping-Hung [1 ]
Chang-Lioa, Kuei-Shu [1 ]
Wu, Tai-Yu [1 ]
Wang, Tien-Ko [1 ]
Tzeng, Pei-Jer [2 ]
Lin, Cha-Hsin [2 ]
Lee, Lung-Sheng [2 ]
Tsai, Ming-Jin [2 ]
机构
[1] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu, Taiwan
[2] Ind Technol Res Inst, Optoelect Res Labs, Hsinchu, Taiwan
来源
2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2 | 2007年
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:76 / +
页数:2
相关论文
共 3 条
[1]   Design considerations in scaled SONOS nonvolatile memory devices [J].
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[2]   Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer [J].
Chen, TS ;
Wu, KH ;
Chung, H ;
Kao, CH .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (04) :205-207
[3]   VARIOT: A novel multilayer tunnel barrier concept, for low-voltage nonvolatile memory devices [J].
Govoreanu, B ;
Blomme, P ;
Rosmeulen, M ;
Van Houdt, J ;
De Meyer, K .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (02) :99-101