18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs

被引:9
作者
Weber, Olivier [1 ]
Min, Doohong [2 ]
Villaret, Alexandre [1 ]
Park, Jinha [2 ]
Lee, Ilmin [2 ]
Vandenbossche, Eric [1 ]
Kim, Dohun [2 ]
Yun, Jiyoung [2 ]
Park, Jinwoo [2 ]
Lee, Minuk [2 ]
Kang, Jinseok [2 ]
Lee, Hyunjong [2 ]
Choi, Youngju [2 ]
Kim, Inhwan [2 ]
Kim, Joochan [2 ]
Janardan, Dhori Kedar [1 ]
Haendler, Sebastien [1 ]
Elghouli, Salim [1 ]
Puget, Sophie [1 ]
Bernicot, Christophe [1 ]
Bernard, Emilie [1 ]
Wacquant, Francois [1 ]
Nimsgern, Fabien [1 ]
Choi, Joonhyuk [2 ]
Maeda, Shigenobu [2 ]
Lee, Jongho [2 ]
Arnaud, Franck [1 ]
机构
[1] STMicroelect, 850 Rrue Jean Monnet, F-38926 Crolles, France
[2] Samsung Elect Co Ltd, Foundry Div, 1 Samsung Ro, Yongin, Gyeonggi Do, South Korea
来源
2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | 2022年
关键词
D O I
10.1109/IEDM45625.2022.10019397
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We successfully developed new devices and new features in the 18nm FDSOI technology for addressing the low power and the low leakage demands of Micro-Controller Units (MCUs). In a quadruple fully mixable Vt offer, 80% speed enhancement and 2x leakage reduction are demonstrated at 0.6V V-dd vs the fastest and vs the less-leaky 28nm FDSOI devices, respectively. Low leakage device options have been built for all device families of this Triple Gate Oxide (TGO) platform (i.e thin: SG - medium: EG - thick: eZG), achieving 10pA/mu m for SG/EG transistors and 1pA/mu m Idoff for 3.3V eZG ones without adding any mask nor process cost. For SRAM, the high-density 0.102 mu m(2) SRAM bitcell has been carefully optimized and, in addition, an innovative Zero-power 0.532 mu m(2) SRAM (ZpSRAM) is proposed for the first time. As a result, record-low retention leakage of 0.6pA/cell and 30fA/cell are reported respectively for those two bitcells, completing the list of benefits brought to the 18nm FDSOI device suite to fulfill ULP/ULL design requirements.
引用
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页数:4
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