A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate

被引:9
作者
Tsai, Yi-Hung [1 ]
Lin, Kai-Chun [1 ]
Kuo, Cheng-Hsiung [2 ]
Chih, Yue-Der [2 ]
Lin, Chrong-Jung [1 ]
King, Ya-Chin [1 ]
机构
[1] Natl Tsing Hua Univ, Inst Elect Engn, Hsinchu 300, Taiwan
[2] Taiwan Semicond Mfg Co Ltd, Non Volatile Memory Lib Dept, Hsinchu 300, Taiwan
关键词
Logic-NVM; one-time programmable (OTP); p-channel; 2-bit/cell; CMOS; RETENTION; CHARGE;
D O I
10.1109/LED.2009.2028442
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This letter presents a new 2-bit/cell contact-gated one-time-programmable (OTP) device, which is demonstrated in a 90-nm CMOS logic process. The cell is programmed by electron injection and storage in the contact-etch-stop-layer (CESL) nitride film. A novel contact gate is introduced to serve as a select transistor, which allows the cell to exhibit good immunity against program and read disturbances. The 2-bit/cell operation is achieved by selectively injecting charges into the CESL on either side of the contact gate through channel-hot-electron operation. With a unit bit area of 13.8 F-2, this nitride-based contact-gated OTP memory is highly feasible for advanced logic applications.
引用
收藏
页码:1090 / 1092
页数:3
相关论文
共 13 条
  • [1] A 32-KB standard CMOS antifuse one-time programmable ROM embedded in a 16-bit microcontroller
    Cha, Hyouk-Kyu
    Yun, Ilhyun
    Kim, Jinbong
    So, Byeong-Cheol
    Chun, Kanghyup
    Nam, Ilku
    Lee, Kwyro
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (09) : 2115 - 2124
  • [2] NROM: A novel localized trapping, 2-bit nonvolatile memory cell
    Eitan, B
    Pavan, P
    Bloom, I
    Aloni, E
    Frommer, A
    Finzi, D
    [J]. IEEE ELECTRON DEVICE LETTERS, 2000, 21 (11) : 543 - 545
  • [3] NVM characteristics of single-MOSFET cells using nitride spacers with gate-to-drain NOI
    Hsieh, CS
    Kao, PC
    Chin, CS
    Hon, CH
    Fan, CC
    Kung, WC
    Wang, ZW
    Jeng, ES
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (11) : 1811 - 1817
  • [4] A new self-aligned nitride MTP cell with 45nm CMOS fully compatible process
    Huang, Chia-En
    Chen, Hsin-Ming
    Lai, Han-Chao
    Chen, Ying-Je
    King, Ya-Chin
    Lin, Chrong Jung
    [J]. 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 91 - +
  • [5] A 0.26-μm2 U-Shaped nitride-based programming cell on pure 90-nm CMOS technology
    Lai, Han-Chao
    Cheng, Kai-Yuan
    King, Ya-Chin
    Lin, Chrong-Jung
    [J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28 (09) : 837 - 839
  • [6] Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric
    Lusky, E
    Shacham-Diamand, Y
    Bloom, I
    Eitan, B
    [J]. IEEE ELECTRON DEVICE LETTERS, 2002, 23 (09) : 556 - 558
  • [7] Peng J., 2006, P 21 IEEE NVSMW, P24
  • [8] Embedded flash memory for security applications in a 0.13μm CMOS logic process
    Raszka, J
    Advani, M
    Tiwari, V
    Varisco, L
    Der Hacobian, N
    Mittal, A
    Han, M
    Shirdel, A
    Shubat, A
    [J]. 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 46 - 47
  • [9] Rosenberg J, 2005, 2005 Non-Volatile Memory Technology Symposium, Proceedings, P19
  • [10] A precision CMOS amplifier using floating.-gate transistors for offset cancellation
    Srinivasan, Venkatesh
    Serrano, Guillermo J.
    Gray, Jordan
    Hasler, Paul
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (02) : 280 - 291