Single mask metal-insulator-metal (MIM) capacitor with copper damascene metallization for sub-0.18μm mixed mode signal and system-on-a-chip (SoC) applications

被引：15

作者：

Liu, RC ^{[1
]}

Lin, CY ^{[1
]}

Harris, E ^{[1
]}

Merchant, S ^{[1
]}

Downey, SW ^{[1
]}

Weber, G ^{[1
]}

Ciampa, NA ^{[1
]}

Tai, W ^{[1
]}

Lai, YC ^{[1
]}

Morris, MD ^{[1
]}

Bower, JE ^{[1
]}

Miner, JF ^{[1
]}

Frackoviak, J ^{[1
]}

Mansfield, W ^{[1
]}

Barr, D ^{[1
]}

Keller, R ^{[1
]}

Chang, CP ^{[1
]}

Pai, CS ^{[1
]}

Rogers, SN ^{[1
]}

Gregor, R ^{[1
]}

机构：

[1] Bell Labs, Lucent Technol, Murray Hill, NJ 07974 USA

来源：

PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2000年

关键词：

D O I：

10.1109/IITC.2000.854297

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A one-mask metal-insulator-metal (MIM) capacitor wing damascene Cu as the bottom electrode has been developed. Using a PECVD SiN as both the capacitor dielectric and the diffusion barrier for Cu we have demonstrated, for the first time. the achieving of low leakage, high linearity MIM capacitors directly on Cu. The leakage and breakdown characteristics of the MIM capacitor depend strongly on both the surface conditions of the damascened Cu and on the PECVD SiN. We found that multilayered SiN is superior than single layer SiN, and Cu CMP plays an important role. However, the inevitable dishing on large area capacitors during Cu CMP shows little impact on the electrical characteristics.

引用

页码：111 / 113

页数：3