Energy minimization method for optimal energy-delay extraction

被引：7

作者：

Dao, HQ ^{[1
]}

Zeydel, BR ^{[1
]}

Oklobdzija, VG ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, ACSEL Lab, Davis, CA 95616 USA

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257101

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In evaluating a design, it is critical to extract the best energy-delay curve, often performed with optimization tools. Such a curve can be quickly obtained from our proposed numerical method where the energy at each delay target is minimized by redistribution of gate sizes to balance delay and energy consumption among different stages of the design. Compared to delay-optimized solution, the resulting energy saving is significant, 30%-50% depending on delay target and design. The results are confirmed with simulation, using Fujitsu's 0.11 mum, 1.2V CMOS technology.

引用

页码：177 / 180

页数：4

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