Using the Charge Recycling Technique for Low Power PLA Design

被引：0
|
作者：
Xiao, Chiuan-Tai [1 ]
Wei, Kai-Cheng [2 ]
机构：
[1] Natl Changhua Univ Educ, Grad Inst Integrated Circuit Design, 1 Jin De Rd, Changhua, Taiwan
[2] Natl Changhua Univ Educ, Dept Comp Sci & Informat Engn, Changhua 500, Taiwan
来源：
2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | 2010年
关键词：
SINGLE-CLOCK CMOS; HIGH-SPEED;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35 mu m CMOS process technology.
引用
收藏
页码：347 / 350
页数：4
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