A 0.10μm CMOS, 1.2V, 2GHz phase-locked loop with gain compensation VCO

被引：12

作者：

Minami, K ^{[1
]}

Fukaishi, M ^{[1
]}

Mizuno, M ^{[1
]}

Onishi, H ^{[1
]}

Noda, K ^{[1
]}

Imai, K ^{[1
]}

Horiuchi, T ^{[1
]}

Yamaguchi, H ^{[1
]}

Sato, T ^{[1
]}

Nakamura, K ^{[1
]}

Yamashina, M ^{[1
]}

机构：

[1] NEC Corp Ltd, Syst Devices & FUndamental Res, Sagamihara, Kanagawa 2291198, Japan

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929758

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 1.2-V, 2-GHz low-jitter phase-locked loop (PLL) using a gain compensation VCO. In order to improve the jitter performance of PLLs, we have developed a new VCO that has a low gain and a linear V-f characteristic. The characteristics of our VCO are achieved by using three V-I converters and blending their different characteristics. The PLL is fabricated in 0.10-mum CMOS technology. Its loop filter includes MOS transistors for I/O in order to suppress the influence of gate leakage current. At 1.2V, 2-GHz operation, measured rms and peak-to-peak jitter of the PLL are 2.8 and 21 ps, respectively.

引用

页码：213 / 216

页数：4

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