VLSI DESIGN OF AREA-EFFICIENT MEMORY ACCESS ARCHITECTURES FOR QUASI-CYCLIC LDPC CODES

被引：0

作者：

Shieh, Ming-Der ^{[1
]}

Fang, Shih-Hao ^{[1
]}

Tang, Shing-Chung ^{[1
]}

Yang, Der-Wei ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 701, Taiwan

来源：

2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) | 2011年

关键词：

PARITY-CHECK CODES; DECODER DESIGN;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.

引用

页码：242 / 246

页数：5

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