Configurable, high throughput, irregular LDPC decoder architecture: Tradeoff analysis and implementation

被引：25
作者：
Karkooti, Marjan [1 ]
Radosavljevic, Predrag [1 ]
Cavallaro, Joseph R. [1 ]
机构：
[1] Rice Univ, Dept Elect & Comp Engn, Houston, TX 77005 USA
来源：
IEEE 17TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/ASAP.2006.23
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper presents a novel flexible decoder architecture for irregular LDPC codes that supports twelve combinations of code lengths -648, 1296, 1944 bits- and code rates-1/2, 2/3,3/4,5/6- based on the IEEE 802.11n standard. All the codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. A prototype of the LDPC decoder has been implemented and tested on a Xilinx FPGA and has been synthesized for ASIC.
引用
收藏
页码：360 / +
页数：2
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