Testing for interconnect crosstalk defects using on-chip embedded processor cores

被引：0
作者：
Chen, L [1 ]
Bai, XL [1 ]
Dey, S [1 ]
机构：
[1] Univ Calif San Diego, Dept ECE, La Jolla, CA 92093 USA
来源：
38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001 | 2001年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers, Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.
引用
收藏
页码：317 / 320
页数：4
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