Reconfigurable embedded media processors

被引:0
|
作者
Panchanathan, S [1 ]
机构
[1] Arizona State Univ, Dept Comp Sci & Engn, Collaborat Program Ubiquitous Comp, CUbiC, Tempe, AZ 85233 USA
来源
CONFERENCE PROCEEDINGS OF THE 2001 IEEE INTERNATIONAL PERFORMANCE, COMPUTING, AND COMMUNICATIONS CONFERENCE | 2001年
关键词
D O I
10.1109/IPCCC.2001.918666
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The rapid proliferation of embedded multimedia applications necessitates efficient implementations which satisfy the computing demands of the various media processing algorithms. Several hardware and software solutions for media processing have appeared in the recent literature. The complexity, variety of techniques and tools associated with multimedia processing points to the opportunities for reconfigurable computing devices. These devices will be able to adapt the underlying hardware dynamically in response to changes in the input data or processing environment. In order to understand the static and dynamic nature of media processing techniques, there is a need to first perform a detailed complexity analysis on the set of candidate algorithms that encompass multimedia processing. This in turn will facilitate the design of a reconfigurable embedded hardware system. In this paper, we present a summary of the various implementation alternatives for media processing followed by the proposed approach for designing reconfigurable processors. We have chosen the latest multimedia standard namely, MPEG 4 as an example to demonstrate the potential for reconfigurability.
引用
收藏
页码:293 / 298
页数:6
相关论文
共 50 条
  • [1] Microcoded reconfigurable embedded processors: Current developments
    Wong, S
    Vassiliadis, S
    Cotofana, S
    EMBEDDED PROCESSOR DESIGN CHALLENGES: SYSTEMS, ARCHITECTURES, MODELLING, AND SIMULATION - SAMOS, 2002, 2268 : 207 - 223
  • [2] Recent trends on media processors for embedded systems
    Onoye, Takao
    Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers, 2009, 63 (09): : 1185 - 1187
  • [3] Fine-Grain Reconfigurable Functional Unit for Embedded Processors
    Cardarilli, Gian Carlo
    Di Nunzio, Luca
    Fazzolari, Rocco
    Re, Marco
    2011 CONFERENCE RECORD OF THE FORTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS (ASILOMAR), 2011, : 488 - 492
  • [4] An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors
    Tamimi, Sajjad
    Ebrahimi, Zahra
    Khaleghi, Behnam
    Asadi, Hossein
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 38 (03) : 466 - 479
  • [5] Efficient implementation of elliptic curve cryptography (ECC) on embedded media processors
    Hu, Y
    Li, Q
    Huang, L
    Kuo, CCJ
    VISUAL COMMUNICATIONS AND IMAGE PROCESSING 2004, PTS 1 AND 2, 2004, 5308 : 132 - 143
  • [6] Fusing mainstream and media processors to solve embedded imaging applications affordably
    Rinn, R
    Fleischer, C
    EMERGING APPLICATIONS OF COMPUTER VISION - 25TH AIPR WORKSHOP, 1997, 2962 : 236 - 241
  • [7] The molen compiler for reconfigurable processors
    Panainte, Elena Moscu
    Bertels, Koen
    Vassiliadis, Stamatis
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2007, 6 (01) : 6
  • [8] A survey on dynamically reconfigurable processors
    Amano, Hideharu
    IEICE TRANSACTIONS ON COMMUNICATIONS, 2006, E89B (12) : 3179 - 3187
  • [9] The AMIDAR Class of Reconfigurable Processors
    Stephan Gatzka
    Christian Hochberger
    The Journal of Supercomputing, 2005, 32 : 163 - 181
  • [10] The AMIDAR class of reconfigurable processors
    Gatzka, S
    Hochberger, C
    JOURNAL OF SUPERCOMPUTING, 2005, 32 (02): : 163 - 181