Synthesizing Hardware from Dataflow Programs

被引：32

作者：

Janneck, Joern W. ^{[2
]}

Miller, Ian D. ^{[3
]}

Parlour, David B. ^{[4
]}

Roquier, Ghislain ^{[5
]}

Wipliez, Matthieu ^{[1
]}

Raulet, Mickael ^{[1
]}

机构：

[1] IETR INSA, CNRS, UMR 6164, F-35043 Rennes, France

[2] Xilinx Inc, San Jose, CA 95124 USA

[3] siXis Inc, Res Triangle Pk, NC 27709 USA

[4] Tabula Inc, Santa Clara, CA 95054 USA

[5] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

来源：

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2011年 / 63卷 / 02期

关键词：

Dataflow; CAL; Reconfigurable Video Coding; MPEG; High-level synthesis;

D O I：

10.1007/s11265-009-0397-5

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

引用

页码：241 / 249

页数：9

共 50 条

[41] Algorithm-Hardware Co-design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA
Kenter, Tobias
Shambhu, Adesh
Faghih-Naini, Sara
Aizinger, Vadym
PROCEEDINGS OF THE PLATFORM FOR ADVANCED SCIENTIFIC COMPUTING CONFERENCE (PASC '21), 2021,
[42] From Monolith to Microservices: A Dataflow-Driven Approach
Chen, Rui
Li, Shanshan
Li, Zheng
2017 24TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE (APSEC 2017), 2017, : 466 - 475
[43] SoC memory hierarchy derivation from dataflow graphs
Fischaber, Scott
Woods, Roger
McAllister, John
2007 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, VOLS 1 AND 2, 2007, : 469 - 474
[44] Automated Extraction of Scenario Sequences from Disciplined Dataflow Networks
Siyoum, Firew
Geilen, Marc
Eker, Johan
von Platen, Carl
Corporaal, Henk
2013 ELEVENTH ACM/IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CODESIGN (MEMOCODE 2013), 2013, : 47 - 56
[45] Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs
Ashcraft, Matthew B.
Goeders, Jeffrey
2019 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2019), 2019, : 54 - 62
[46] Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs
Ashcraft, Matthew B.
Goeders, Jeffrey
2018 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2018), 2018, : 357 - 360
[47] Efficient code synthesis from extended dataflow graphs for multimedia applications
Oh, H
Ha, S
39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 275 - 280
[48] A dataflow-driven approach to identifying microservices from monolithic applications
Li, Shanshan
Zhang, He
Jia, Zijia
Li, Zheng
Zhang, Cheng
Li, Jiaqi
Gao, Qiuya
Ge, Jidong
Shan, Zhihao
JOURNAL OF SYSTEMS AND SOFTWARE, 2019, 157
[49] Hardware and Software Generation from Large Actor Machines in Streaming Applications
Callanan, Gareth
Gruian, Flavius
39TH ANNUAL ACM SYMPOSIUM ON APPLIED COMPUTING, SAC 2024, 2024, : 142 - 150
[50] The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design
Sau, Carlo
Fanni, Tiziana
Rubattu, Claudio
Raffo, Luigi
Palumbo, Francesca
MICROPROCESSORS AND MICROSYSTEMS, 2021, 80

← 1 2 3 4 5 →