Strain enhancement in spacerless N-channel FinFETs with Silicon-Carbon Source and Drain stressors

被引：1

作者：

Liow, Tsung-Yang ^{[1
,2
]}

Tan, Kian-Ming ^{[1
]}

Lee, Rinus T. P. ^{[1
]}

Zhu, Ming ^{[1
]}

Hoe, Keat-Mun ^{[2
]}

机构：

[1] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 117576, Singapore

[2] Inst Microelect, Singapore 117685, Singapore

来源：

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2007年

关键词：

D O I：

10.1109/ESSDERC.2007.4430901

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

By removing the SiN gate spacers in n-channel FinFETs with Silicon-Carbon (SiC) Source and Drain (S/D) stressors, the mechanical stress equilibrium is perturbed. Higher tensile channel stress can be achieved, after the transistor structure attains mechanical equilibrium once again after spacer removal. This stress increase results in up to similar to 15 % further I-Dsat enhancement over strained SiC S/D FinFETs with spacers intact. Peak G(m) is enhanced by similar to 33 %.

引用

页码：151 / +

页数：2

共 7 条

[1] CHEN X, 2006, S VLSI TECH, P74
[2] Performance improvement of tall triple gate devices with strained SiN layers
Collaert, N
De Keersgieter, A
Anil, KG
Rooyackers, R
Eneman, G
Goodwin, M
Eyckens, B
Sleeckx, E
de Marneffe, JF
De Meyer, K
Absil, P
Jurczak, M
Biesemans, S
[J]. IEEE ELECTRON DEVICE LETTERS, 2005, 26 (11) : 820 - 822
[3] COLLAERT N, 2006, S VLSI TECHN, P64
[4] KAVALIEROS J, 2006, S VLSI TECH, P62
[5] Liow T.-Y., 2006, S VLSI TECH, P68
[6] LIOW TY, 2006, S VLSI TECH, P473
[7] Verheyen P, 2005, 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P194

← 1 →