SCALABLE AND SYSTOLIC DUAL BASIS MULTIPLIER OVER GF(2m)

This work presents a novel low-complexity scalable and systolic architecture for dual basis multiplications over GF(2(m)). The proposed architecture is derived by utilizing the block Hankel matrix-vector representation and is feasible for finite fields generated by irreducible trinomials. By selecting an. appropriate digit size d, the proposed scalable architecture can achieve a satisfactory trade-off between throughput performance and hardware complexity for implementing cryptographic schemes such as ECDSA in resource-constrained environments such as smart cards and embedded systems. Analytical results indicate that both area and time-area complexities of the proposed architecture are significantly lower than those of the non-scalable architecture schemes. Furthermore, due to its features of regularity, modularity and concurrency, the proposed architecture is highly feasible for VLSI implementations.