Performance Analysis of 1 bit Full Adder Using GDI Logic

被引：0

作者：

Mohan, Shoba ^{[1
]}

Rangaswamy, Nakkeeran ^{[1
]}

机构：

[1] Pondicherry Univ, Sch Engn & Technol, Dept Elect Engn, Pondicherry, India

来源：

2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES) | 2014年

关键词：

low power; adder; full swing; LOW-POWER; CMOS; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper focuses on the design of 1 bit full adder circuit using Gate Diffusion Input Logic. The proposed adder schematics are developed using DSCH2 CAD tool, and their layouts are generated with Microwind 3 VLSI CAD tool. A 1 bit adder circuits are analyzed using standard CMOS 120nm features with corresponding voltage of 1.2V. The Simulated results of the proposed adder is compared with those of Pass transistor, Transmission Function, and CMOS based adder circuits. The proposed adder dissipates low power and responds faster.

引用

页数：4

共 50 条

[31] Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell
Ayush Kanojia
Sachin Agrawal
Rohit Lorenzo
Wireless Personal Communications, 2023, 129 : 1097 - 1111
[32] High-performance approximate half and full adder cells using NAND logic gate
Waris, Haroon
Wang, Chenghua
Liu, Weiqiang
IEICE ELECTRONICS EXPRESS, 2019, 16 (06):
[33] On the design of low power 1-bit full adder cell
Maeen, Mehrdad
Foroutan, Vahid
Navi, Keivan
IEICE ELECTRONICS EXPRESS, 2009, 6 (16): : 1148 - 1154
[34] High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell
Kandpal, Jyoti
Tomar, Abhishek
Agarwal, Mayur
Sharma, K. K.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (06) : 1413 - 1422
[35] Design of 1-bit Full Adder using β-Driven Threshold Element
Paul, Madhusmita
Kapoor, Neha
Modak, Rohini
Paul, Tathagata
Chaudhuri, Rajarshi Roy
Chowdhury, Subhajit Dutta
Sarkar, Mili
2017 1ST INTERNATIONAL CONFERENCE ON ELECTRONICS, MATERIALS ENGINEERING & NANO-TECHNOLOGY (IEMENTECH), 2017,
[36] AN IMPLEMENTATION OF 1-BIT LOW POWER FULL ADDER BASED ON MULTIPLEXER AND PASS TRANSISTOR LOGIC
Parihar, Rajesh
Tiwari, Nidhi
Mandloi, Aditya
Kumar, Binod
2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
[37] An Energy Efficient Logic Approach to Implement CMOS Full Adder
Kumar, Pankaj
Sharma, Rajender Kumar
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (05)
[38] A SURVEY OF LOW POWER HIGH SPEED ONE BIT FULL ADDER
Chore, N. M.
Mandavgane, R. N.
RECENT ADVANCES IN NETWORKING, VLSI AND SIGNAL PROCESSING, 2010, : 302 - +
[39] A 4-bit CMOS Full Adder of 1-bit Hybrid 13T Adder With A New SUM Circuit
Jie, Lee Shing
Ruslan, Siti Hawa
PROCEEDINGS OF THE 14TH IEEE STUDENT CONFERENCE ON RESEARCH AND DEVELOPMENT (SCORED), 2016,
[40] Implementation of 4-bit carry select adder using Diode free Adiabatic Logic (DFAL)
Singh, Sanjay
Srinivasarao, K.
2015 IEEE 2ND INTERNATIONAL CONFERENCE ON RECENT TRENDS IN INFORMATION SYSTEMS (RETIS), 2015, : 481 - 484

← 1 2 3 4 5 →