Performance Analysis of 1 bit Full Adder Using GDI Logic

被引：0

作者：

Mohan, Shoba ^{[1
]}

Rangaswamy, Nakkeeran ^{[1
]}

机构：

[1] Pondicherry Univ, Sch Engn & Technol, Dept Elect Engn, Pondicherry, India

来源：

2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES) | 2014年

关键词：

low power; adder; full swing; LOW-POWER; CMOS; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper focuses on the design of 1 bit full adder circuit using Gate Diffusion Input Logic. The proposed adder schematics are developed using DSCH2 CAD tool, and their layouts are generated with Microwind 3 VLSI CAD tool. A 1 bit adder circuits are analyzed using standard CMOS 120nm features with corresponding voltage of 1.2V. The Simulated results of the proposed adder is compared with those of Pass transistor, Transmission Function, and CMOS based adder circuits. The proposed adder dissipates low power and responds faster.

引用

页数：4

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